The present invention relates to a semiconductor memory and, more particularly, to a technique which is effective when used in a dynamic RAM (i.e., Random Access Memory) capable of a nibble mode operation.
In the dynamic RAM, for example, there has been proposed in addition to a one-bit access system an access system of the so-called "nibble mode" (which should be referred to "Hitachi Memory Data Book", pp. 307 to 320, issued by Hitachi, Ltd., in September 1983, for example). In that nibble mode, four-bit data is output serially by a selection signal which is generated by the counted output of a shift register or binary counter made operative in synchronism with a column address strobe signal CAS.
In the aforementioned nibble mode, when other four-bit data is read out subsequently to the reading operation of the preceding four-bit data, it becomes necessary that a column selecting circuit has to be once reset to supply an initial address. In this case, however, the interval between the reading operations of every four-bits takes a relatively long time.